1. Field of the Invention
The present invention relates to a driving system and method used for a display panel, and more particularly, to a driving system and method for driving a display panel and a display device thereof.
2. Description of the Prior Art
Conventionally, a display device such as a liquid crystal display (LCD) device includes a display panel driven by a gate driving circuit and a source driving circuit. A timing controller is coupled to the gate driving circuit and the source driving circuit, and generates gate control signals (a.k.a. scan signals) to control the timing that data voltage signals from the source driving circuit output to the display panel. The timing controller, the source driving circuit and the gate driving circuit may be implemented in a single or separate semiconductor chips.
Generally, a source driving circuit is implemented to be capable of driving different display panels of different resolutions for a variety of devices, such as tablets, mobile phones and car navigation device, and the horizontal resolution of the display panel may be less than the maximum resolution that the source driving circuit can support. For example, the source driving circuit has 1280 data voltage output channels (abbreviated to output channels, which are referred to as output pins of a semiconductor chip where the source driving circuit is integrated), while the horizontal resolution of the display panel may be 960 pixels. In a case that each output channel may selectively output (via a multiplexer) data voltage signals to three data lines of the display panel, 320 extra output channels of the source driving circuit, i.e., 1280−960=320, are not coupled to data lines of the display panel, which means that the 320 output channels are configured to be dummy channels.
Since a source diving circuit should be adaptive to display panels of different horizontal resolutions, various methods are developed to adjust the number of dummy channels. A conventional method is to dispose additional connecting wires between different shift registers of a source driving circuit, allowing a start pulse to skip over several shift registers, and in such a way those output channels corresponding to the skipped shift registers are configured as the dummy channels.
Please refer to FIG. 1, which is a schematic diagram of a display device 10 according to the prior art. The display device 10 includes a display panel 100 and a driving system 110 for driving the display panel 100. The display panel 100 includes a plurality of pixel units. The driving system 110 includes a timing controller 112 and a source driving circuit. The source driving circuit includes a shift register circuit including a plurality of shift registers, a latch circuit, a level shifter circuit, a digital-to-analog converter (DAC) circuit, an output buffer circuit for generating data voltage signals, and a plurality of output channels coupled to the output buffer circuit through which the data voltage signals are outputted to data lines (not shown) of the display panel 100 to drive the pixel units. The output channels may be referred to as output pins of the semiconductor chip of the driving system 110. The (valid) output channels are one-to-one or one-to-many coupled to data lines of the display panel 100. The timing controller 112 may transmit a start pulse to the shift register circuit and the start pulse is sequentially shifted though the shift registers based on a clock signal (not shown in FIG. 1). A shift register is able to enable a corresponding latch unit to sample pixel data corresponding to an output channel. In FIG. 1, a connecting wire W1 is disposed to connect between two nonadjacent shift registers, which allows the start pulse to skip over several shift registers such that output channels corresponding to the skipped shift registers are configured as dummy channels. The dummy channels are not coupled to data lines of the display panel 100.
FIG. 2A is a schematic diagram of a driving system 20, which gives a clear example regarding to the connecting wire W1 of FIG. 1. In FIG. 2A, only a partial circuit of the driving system 20, including a timing controller 212 and shift registers SR01-SR16 connected in series, is illustrated. The connecting wire W1 is connected between two nonadjacent shift registers, SR04 and SR13, allowing a start pulse SP to skip over shift registers SR05-SR12 such that output channels corresponding to the shift registers SR05-SR12 are configured as the dummy channels.
FIG. 2B and FIG. 2C illustrate the same circuit as in FIG. 2A, with different transmission directions of a start pulse SP when dummy channels are configured. In FIG. 2B, the timing controller 212 transmits the start pulse SP to the shift register SR01, and the start pulse SP is shifted sequentially. After the start pulse SP is shifted to the shift register SR04, the start pulse SP is then shifted to the shift register SR13 through the connecting wire W1 (as a bypass). In FIG. 2C, the timing controller 212 transmits the start pulse SP to the shift register SR16, and the start pulse SP is shifted sequentially. After the start pulse SP is shifted to the shift register SR13, the start pulse SP is then shifted to the shift register SR04 through the connecting wire W1. By using the connecting wire W1, the source driving circuit having 16 output channels may be able to drive a display panel with horizontal resolution of 8 pixels.
In order to support different horizontal resolutions of different display panels, a source driving circuit of a conventional driving system includes a plenty of connecting wires like the connecting wire W1 shown in FIG. 1 and FIGS. 2A-2C to skip different number of shift registers so as to configure different number of dummy channels. For example, a source driving circuit having 1280 output channels can also support horizontal resolutions of 720 pixels and 960 pixels by using two additional connecting wires. That is, one additional connecting wire skips over 320 shift registers so that 320 (i.e., 1280−960) dummy channels are configured, and the other additional connecting wire skips over 560 shift registers so that 560 (i.e., 1280−720) dummy channels are configured. These additional wire connections consume circuit layout area and reduce layout flexibility. Thus, there is a need to provide a more efficient method and a source driving circuit which is adaptive to more horizontal resolutions, and thus adaptive to more types of display panels.